The present invention generally relates to a fabricating technology of a semiconductor device, and more particularly, to a semiconductor device having a fin transistor and a method for fabricating the same.
Presently, since semiconductor devices have become highly integrated, typical 2-dimensional transistors encounter limitations. In that, 2-dimensional transistors are not available for high-speed devices because they cannot meet a demand for high current drivability.
To overcome such limitations, a variety of transistors having a 3-dimensional structure are being proposed, of which one is a fin field effect transistor (fin-FET, hereinafter referred to as a fin transistor). The fin transistor uses three sides as a channel to improve current drivability. On the contrary, the fin transistor is difficult to secure a threshold voltage greater than a certain level due to its three-side channels. Therefore, it is difficult to apply the fin transistor to a cell transistor of a memory device such as a dynamic random access memory (DRAM) because off-leakage characteristics are deteriorated unless securing a threshold voltage greater than a predetermined level in a memory device such as the DRAM.
Accordingly, a technique, which is capable of increasing a threshold voltage of a fin transistor, is required for employing the fin transistor as a cell transistor of the memory device. One of The techniques that has been suggested is a polysilicon layer, doped with p-type impurities such as boron (B), used as a gate electrode of the fin transistor instead of a typical polysilicon layer doped with n-type impurities such as phosphorous (P). Hereinafter, for convenience of the description, the polysilicon layer doped with p-type impurities will be referred to as a P+ polysilicon layer and the polysilicon layer doped with n-type impurities will be referred to as a N+ polysilicon layer. Theoretically, since the P+ polysilicon layer has a work function greater than N+ polysilicon layer by approximately 1.1 eV, it is possible to increase the threshold voltage of the fin transistor by a certain voltage level, e.g., approximately 0.8 V to approximately 1.0 V, by substituting the P+ polysilicon gate electrode for the N+ polysilicon gate electrode. A typical semiconductor device having such a fin transistor is illustrated in FIG. 1.
FIG. 1 illustrates a cross-sectional view of a semiconductor device having a typical fin transistor. Here, the semiconductor device, particularly a memory device, includes a cell region A and a peripheral region B. The cell region is configured with an NMOS transistor. The peripheral region B is divided into an NMOS peripheral region B1 and a PMOS peripheral region B2. A fin transistor having a typical structure is formed in the cell region A of the memory device, whereas a general planar transistor is formed in the peripheral region B.
As illustrated in FIG. 1, an isolation layer 12 is formed in a substrate 11 to define a first active region 11A in the cell region A, a second active region 11B in an NMOS peripheral region B1 of a peripheral circuit, and a third active region 11C in a PMOS peripheral region B2 of the peripheral circuit. The first, second and third active regions 11A, 11B and 11C are separated from one another by the isolation layer 12. A portion of the isolation layer 12 in the cell region A where a gate electrode will pass, is removed through masking and etching processes to form a gap G, thus exposing a top surface and portions of sidewalls of the first active region 11A. The first active region 11A vertically protrudes from the substrate 11 in virtue of the gap G. This protruding first active region serves as a fin active region in the fin transistor.
Second and third gate insulation patterns 13B and 13C and second and third gate conductive patterns 14B and 14C are sequentially formed over the second and third active regions 11B and 11C, respectively. The second gate conductive pattern 14B of the NMOS peripheral region B1 is formed of N+ polysilicon having a low work function, and the gate electrode 14C of the PMOS peripheral region B2 is formed of P+ polysilicon having a high work function.
A first gate insulation pattern 13A is formed on a surface of the exposed first active region 11A. A first gate conductive pattern 14A is formed on the first gate insulation pattern 13A and the isolation layer 12 in the cell region A such that it overlaps the gap G while crossing the first active region 11A. The first gate conductive pattern 14A in the cell region A is formed of P+ polysilicon, thus increasing the threshold voltage of the fin transistor.
However, the typical semiconductor device has several limitations below. In general, the P+ polysilicon has the work function greater than 4.8 eV and the N+ polysilicon has the work function smaller than 4.4 eV. For instance, it is assumed that there are two cases, i.e., one case where a P+ polysilicon gate having a work function of approximately 5.2 eV is formed on a gate oxide layer and an n-type junction, and the other case where an N+ polysilicon gate having a work function of approximately 4.2 eV is formed on a gate oxide layer and an n-type junction. An energy band diagram of each case is shown in FIG. 2. From these energy band diagrams, it can be observed that a band bending phenomenon becomes severe at an interface between the gate oxide layer and an n-type junction by a degree corresponding to a work function difference (φP-φN) between the P+ polysilicon and the N+ polysilicon in the case of using a P+ polysilicon gate electrode. Further, gate induced drain leakage (GIDL) characteristics become poorer in the case of using the P+ polysilicon gate electrode than the N+ polysilicon gate electrode, thus deteriorating data retention characteristics of a memory device. Therefore, to apply the fin transistor with improved current drivability as the cell transistor of the memory device, it is necessary to develop a technology capable of minimizing a band bending phenomenon while increasing a threshold voltage to a certain level or higher.